Japanese Patent publication No. Hei 7-22431, discloses a mobile communication system in which various transceiver unit (node) sets are connected by single signal lines. Reduction in weight and cost, as well as improvement in communication efficiency, is made possible by simplifying the previous communication system construction.
A circuit diagram of a conventional vehicle communication system for carrying out communication between nodes is shown in FIG. 6. A balanced cable 5 is used as the signal line, which is a twisted pair cable. Node 16 has the same configuration as node 12.
Node 12 is equipped with a transmission circuit 121, a reception circuit 125, and a microcomputer 3. The microcomputer 3 outputs a transmission signal through an output terminal 3a, and this transmission signal acts as a control signal for simultaneously controlling both transistors Q1 and Q3. The reception circuit 125 is equipped with a comparator CP for outputting a reception signal to the input terminal 3b of the microcomputer 3, and resistors R1, R3.
The non-inverting input terminal of the comparator CP (+terminal) is connected to terminal 12a through resistor R1, while the inverting input terminal (-terminal) is connected to terminal 12b through resistor R3.
The transmission circuit 121 is equipped with transistors Q1 and Q3, an inverter N1, an inverter N3, diodes D1-D4, and pull-up resistors RL, RL. The inverter N1 generates a control signal for transistor Q1 by inverting the signal transmitted by the microcomputer 3 through the output terminal 3a. The inverter N3 generates a control signal for transistor Q3 by inverting the control signal output from inverter N1.
A power supply voltage Vdd is applied to the collector of transistor Q1 through a pull-up resistor RL, and the collector of transistor Q3 is connected to ground through a pull-up resistor RL. The core of one cable 5a of the balanced cable 5 is connected to the collector of the transistor Q1 through terminal 12a, while the core of the other cable 5b of the balanced cable 5 is connected to the collector of transistor Q3 through terminal 12b.
In node 12, when the microcomputer 3 sets the output terminal 3a to an H (high) level by transmitting an H level signal, the transistors Q1 and Q3 are both turned off. As a result, the potential of terminal 12a of node 12, the cable 5a that is connected to terminal 12a, and terminal 16a of node 16 connected to the cable 5a becomes the power supply voltage Vdd and has an H level signal. Further, the potential of terminal 12b of node 12, the cable 5b that is connected to terminal 12b and terminal 16b of node 16 connected to the cable 5b becomes the ground potential (0 volts) and has an L level signal.
If a signal is transmitted from node 16 via the balanced cable 5, the comparator CP of node 12 obtains a reception signal (H level signal) by differentially amplifying the signal from the balanced cable 5 and outputs an H level signal to the microcomputer 3.
On the other hand, if the output terminal 3a is set to an L (Low) level as a result of the microcomputer 3 transmitting an L level signal, transistors Q1 and Q3 are turned on together. As a result, the potential of terminal 12a of node 12, the cable 5a that is connected to terminal 12a, and terminal 16a of node 16 connected to the cable 5a becomes the ground potential (0 volts) and has an L level signal. Further, the potential of terminal 12b of node 12, the cable 5b connected to terminal 12b and terminal 16b of node 16 connected to the cable 5b becomes the power supply voltage Vdd and has an H level signal.
If a signal is transmitted from node 16 via the balanced cable 5, the comparator CP of node 12 obtains a reception signal (L level signal) by differentially amplifying the signal from the balanced cable 5 and outputs an L level signal to the microcomputer 3.
When the output terminal 3a switches from an L level to an H level, the rise and fall times of a pulse signal are determined by a pull-up resistor RL, and the distributed capacitance of the signal line, etc. Accordingly, when the signal line is long the pulse signal wave shape is distorted.
In order to solve the aforementioned problems, Japanese Patent Laid open Publication No.-Hei 5-292101 discloses a communication system for a vehicle provided with a pull-up resistor and a signal line connected to a transistor, for carrying out communication between respective nodes through the signal line by controlling the transistor. The transistor is also provided with charge and discharge units for causing the distributed capacitance of the signal line to be discharged by making a stored charge by-pass a pull-up resistor, or causing the distributed capacitance of the signal line to be charged by making a charge by-pass a pull-up resistor. The charge and discharge units cause charge or discharge only for a fixed period of time that is less than 1 bit length of a signal from the instant when the transistor is switched from on to off.
The charge and discharge units provide an improved system over the case where the distributed capacitance of the signal line is discharged by passing a stored charge through a pull-up resistor or charged by passing a charge through a pull-up resistor. The rising (and falling) of a signal can be quickened, and pulse signal waveform distortion can be decreased by use of the charge and discharge units.
Further, since the transistor is in an off state for a time of at least 1 bit length after the transistor switches from on to off, charging or discharging can be carried out by by-passing the pull-up resistor during the transistor off state period. Since the transistor is in the off state, large current does not flow across the transistor collector and emitter, thereby preventing damage to the transistor. This benefit is sustained even when resistance of the charge and discharge unit is low at the time of charge and discharge.
However, if charging or discharging by the charge and discharge units is completed during switching of the reception circuit, noise enters the signal line. Accordingly, there is a danger of the on/off switching of the reception circuit becoming slow due to the effect of a level value of a signal on the signal line momentarily becoming reversed (inverted) and then returning to its original level value.